The present invention relates to a method of producing a ferroelectric memory.
Recently, a semiconductor memory (ferroelectric memory) using a ferroelectric capacitor has been focused as a non-volatile memory. A ferroelectric has a characteristic of holding a bi-polar aligned in a voltage application direction even after a voltage is removed (self-polarization). Accordingly, the ferroelectric memory can be used as a non-volatile memory. A ferroelectric switches polarization thereof at a rate of an order of nano-second. It is also possible to decrease a voltage for switching polarization of the ferroelectric about 2.0 V through optimization of a manufacturing method of a ferroelectric layer. For these reasons, as compared with a flash memory or an EEPROM (electrically erasable programmable read-only memory), the ferroelectric memory has significant advantages in terms of a re-writing speed and an operation voltage. Further, it is possible to re-write the ferroelectric memory more than 1012 times. The ferroelectric capacitor has been commercially available as an RAM (random access memory).
A conventional method of producing a ferroelectric memory will be explained with reference to FIGS. 6(A)–6(C) and 7(A)–7(C) (refer to Patent References 1 to 3).
First, an element separation film 20 is formed on a silicon substrate 10 or a semiconductor substrate to define a memory cell area 12. A first MOSFET 21a, a second MOSFET 21b, and a third MOSFET 21c are formed in the memory cell area 12 and a peripheral circuit area 14 outside the memory cell area 12. The first MOSFET 21a is provided with a gate electrode 25a, an impurity diffused area 28a as a source area, and an impurity diffused area 28b as a drain area. The second MOSFET 21b is provided with a gate electrode 25b, the impurity diffused area 28b as a source area, and an impurity diffused area 28c as a drain area. The third MOSFET 21c is provided with a gate electrode 25c, an impurity diffused area 28d as a source area, and an impurity diffused area 28e as a drain area.
After the first to third MOSFET 21a to 21c are formed on the silicon substrate 10, a silicon oxide film is deposited to form a first interlayer insulating film 35. The impurity diffused areas 28a, 28c, 28d, and 28e are formed in the first interlayer insulating film 35 as the source and drains areas of the first to third MOSFET 21a to 21c. Further, conductive plugs 44 are formed in the first interlayer insulating film 35 for electrically connecting to a ferroelectric capacitor or a metal conductive pattern (FIG. 6(A)). As shown in FIG. 6(A), a bit wiring 34 is formed in the first interlayer insulating film 35 to be connected to the impurity diffused area 28b. 
In the conventional method, the bit wiring 34 is embedded in the first interlayer insulating film 35. Accordingly, it is not necessary to provide a space between the ferroelectric capacitor and the conductive plug of the bit wiring for preventing the conductive plug from contacting the ferroelectric capacitor to be formed in a later step. As a result, it is possible to reduce an area of the element.
In the next step, the first interlayer insulating film 35 is polished with a chemical mechanical polishing (CMP) method. A first conductive layer 60, a ferroelectric layer 62, and a second conductive layer 64 are sequentially laminated on the first interlayer insulating film 35 to form a capacitor forming laminated layer 67a (FIG. 6(B)).
In the next step, the capacitor forming laminated layer 67a is processed with photolithography and dry etching to form ferroelectric capacitors 67 each having a lower electrode 61, a ferroelectric layer 63, and an upper electrode 65 (FIG. 6(C)). The ferroelectric capacitors 67 are electrically connected to the conductive plugs 44 in the memory cell area 12. Normally, after the ferroelectric capacitors 67 are processed with dry etching, an annealing process is performed under oxygen atmosphere (for example, at 750° C. for one minute) to restore damage in the ferroelectric capacitors 67 due to etching. Then, a silicon oxide film is deposited on the first interlayer insulating film 35 to embed the ferroelectric capacitors 67 with a CVD method to form a second interlayer insulating film 52 (FIG. 7(A)).
In the next step, an entire upper surface of the second interlayer insulating film 52 is polished. In this step, when the second interlayer insulating film 52 is polished with the CMP method as is, a portion of the second interlayer insulating film 52 above the memory cell area 12 having a high packaging density tends to protrude relative to a portion of the second interlayer insulating film 52 above the peripheral circuit area 14 having a low packaging density, thereby forming a step portion called a global step in the surface of the second interlayer insulating film 52. In order to eliminate the global step, first, the portion of the second interlayer insulating film 52 above the memory cell area 12 is removed with half etching, so that a height of the portion is reduced in half (FIG. 7(B)). Then, the second interlayer insulating film 52 is polished with the CMP method to flatten the upper surface thereof (FIG. 7(C)).
After the upper surface of the second interlayer insulating film 52 is flattened, additional conductive plugs are formed in the second interlayer insulating film 52 for electrically connecting the conductive plugs 44 of the upper electrodes 65 of the ferroelectric capacitors 67 and the conductive plugs 44 in the peripheral circuit area 14 with a known method. A metal conductive pattern is formed on the second interlayer insulating film 52.
Patent Reference 1; Japanese Patent Publication (Kokai) No. 10-178157
Patent Reference 2; Japanese Patent Publication (Kokai) No. 2002-217381
Patent Reference 3; Japanese Patent Publication (Kokai) No. 2003-86776
In the conventional method described above, the conductive plugs in the memory cell area and the peripheral circuit area are formed in the same step as shown in FIGS. 6(A) to 6(C), thereby causing the following problems. When the ferroelectric capacitors are formed with etching, a vicinity of the surface of the first interlayer insulating film is also etched due to over etching after the lower electrode is formed. During the over etching, the conductive plugs in the peripheral circuit area are exposed in an etching atmosphere, thereby losing the conductive plugs or causing surface roughness. Further, in a state that the conductive plugs made of tungsten are exposed, when the annealing process is performed to restore damage in the ferroelectric capacitors, the conductive plugs are oxidized.
In order to prevent the damage on the conductive plugs described above, in Patent Reference 2, a silicon oxide film is formed on an interlayer insulating film to prevent oxidation of the conductive plugs. In Patent Reference 3, a silicon nitride film is formed on an interlayer insulating film. In the methods disclosed in Patent References 2 and 3, it is necessary to provide an additional step of forming the films to prevent oxidation of the conductive plugs.
In view of the problems described above, an object of the present invention is to provide a method of producing a ferroelectric memory, in which it is possible to prevent damage of a conductive plug when an etching process is performed to form a ferroelectric film or an annealing process is performed to restore a ferroelectric film.
Further objects and advantages of the invention will be apparent from the following description of the invention.